1. Field of the Invention
The invention relates to a computer system and a memory system.
2. Description of the Related Art
A memory including an ECC check function or a parity check function is required for confirming safety in a microcomputer system which is, for example, used in a vehicle. Redundant bits for correcting errors are calculated from data to be written in an ECC memory (Error Check and Correct Memory) having a data correction function by ECC. The calculated redundant bits are stored in a memory core with the data to be written.
Whether there is an error in data (and the redundant bits) or not is detected by the read data and the redundant bits at the time of reading. Error correction is performed when there is an error. For example, error correction is possible when a 1-bit error occurs in the code if the error correction is realized by using a Hamming code. Error detection is possible when a 2-bit error occurs. A parity bit for error detection is calculated from data to be written in the ECC memory having the parity check function. The calculated parity bit is stored in the memory core with data to be written. Whether there is an error in data (and the parity bit) or not is detected by the read data and the parity bit at the time of reading.
There is a case in which an error occurs in the memory and the right instruction code cannot be supplied to a CPU core when the CPU fetches an instruction code from the memory. Such a case causes safety problems in in-vehicle systems and the like, if the CPU is halted to avoid executing the wrong instruction, by causing processing of the microcomputer system to be halted as well. Accordingly, as one method of avoiding the above situation, there is a method in which an external interruption is inputted to the CPU core in response to an error occurrence when the error occurs when accessing the instruction code.
However, in the configuration in which the external interruption is inputted in the CPU in response to the error occurrence, there is a fear that the instruction code in which the error occurred (erroneous instruction code outputted from the memory in which the error occurs and read by the CPU) will be executed before jumping into an interruption routine. In addition, the next instruction fetched by an instruction fetch unit is sometimes not used in a CPU having a pipeline configuration in which the respective operations of instruction fetch, instruction decoding, arithmetic execution, memory access and the like are redundantly executed. The next instruction fetched by an instruction fetch unit would not be used, for example, if an instruction decoding unit determines that a jump instruction decoded at present will jump. When the external interruption is performed in response to the error occurrence at the time of instruction fetch in such case, there is a fear that a pointless interruption will be generated because the error occurred with respect to the instruction which is not actually executed (an instruction following the jump instruction which will not be executed as the result of jump).
In JP-A-03-098129, a method in which an address of an access destination is always stored in a register at every access operation, and an address of the access destination when an error occurs is recorded as a register value by halting storing operation to the register at the point of error occurrence is disclosed.
In Jp-A-01-100636, a method in which, when a memory error or the like occurs at the time of reading, data which can be executed by the CPU is outputted on a bus instead of data having the error and the interruption is performed at the same time is disclosed.